PCB trace width calculator, impedance and via current
Three calculators on one page: a trace width calculator to IPC-2221B, a microstrip impedance calculator that also does striplines, and a via current calculator. Computed in your browser, without an account.
Under every result stands what the width means once the board has to be bought, so the page doubles as a copper weight calculator: which weight can be ordered at all, and where the etch floor runs.
How wide does a PCB trace have to be for a given current?
The short answer for the usual case, an outer layer with 35 µm copper and a 20 K allowed rise: 1 A needs 0.20 mm. Everything else is in the table, and the trace width calculator below takes your own figures.
| Current | 35 µm outer | 35 µm inner | 70 µm outer |
|---|---|---|---|
| 0.5 A | 0.08 | 0.20 | 0.04 |
| 1 A | 0.20 | 0.51 | 0.10 |
| 2 A | 0.51 | 1.33 | 0.26 |
| 3 A | 0.90 | 2.34 | 0.45 |
| 5 A | 1.82 | 4.72 | 0.91 |
| 10 A | 4.72 | 12.29 | 2.36 |
All widths in millimetres, at a 20 K allowed rise to IPC-2221B. Allow only 10 K and the track gets about half again as wide: 0.20 mm for 1 A becomes 0.30 mm.
Shaded values sit below the 0.15 mm etch floor for 35 µm copper. There the current no longer decides the width, manufacturing does: nothing narrower gets drawn.
Widths marked with an asterisk are above 10.16 mm. IPC-2221B is no longer drawn there and the calculation is extending the formula. A track that wide is a plane, and planes are computed differently.
Your track
Length affects resistance, voltage drop and power loss only. It has no bearing on the width. 0 leaves that part out.
0.898 mm wide, 35 µm thick: the track is about 25.6 times as wide as it is high. Copper carries almost entirely through its width, because the thickness is fixed by the weight that was ordered.
What the width means in manufacturing
- 35 µm is a copper weight that can be ordered. It corresponds to 1 oz/ft², one of the steps laminate is stocked in.
- The width sits above the etch floor. At 35 µm copper a standard process etches reliably down to 0.15 mm; KiCad's 0.20 mm default is a design value, not a fabrication limit.
- With 70 µm of copper instead of the weight set above, the same current needs 0.449 mm instead of 0.898 mm. That is the trade a tight area in the layout forces.
- The step is a nominal weight. IPC-4562 lets a nominal 35 µm layer measure as little as 30.9 µm, so anyone designing tight is designing against the label rather than against the thinnest legal foil.
What a heavier copper weight or a finer clearance class costs is not stated here: that is the board fabricator's price structure and it is his. That figure belongs in his quotation.
Two ways on from here
You draw the board
The KiCad plugin reads your board straight out of the design, checks it against the same manufacturing rules the etch floor above comes from, and reports every deviation with its place in the layout.
To the KiCad pluginYou build the assembly
For a whole board PCBoffer checks not one track but every one of them: track widths, clearances, annular rings, holes to the edge. The costing comes out of the same file.
To costing for EMS providersWhat the stack-up costs in the end
Whether a second copper step or one more layer really makes your assembly dearer depends on quantity, laminate and placement, not on a rule of thumb. PCBoffer computes it from your own manufacturing data.
Ask for figures for your own productionWhat the three figures mean
A track is the piece of copper foil left standing after etching. Its width is set by three questions that have nothing to do with each other: how warm it may get, what wave impedance it should have, and what the etching process leaves standing at all.
The width follows from the temperature rise, not from the current
IPC-2221B does not prescribe a current density, it prescribes a temperature. The current warms the copper, the copper passes that heat to air and laminate, and the width is the value at which the two balance at the permitted rise. That is why the equation contains the rise rather than the load: 20 K instead of 10 K saves about a third of the width.
An inner layer is the dearest place for current
The factor in the equation halves from an outer to an inner layer, because a buried track can only shed heat through the laminate. The width does not double as a result, it grows by about 2.6 times, because the exponent 0.725 sits between area and current. Power belongs on the outside.
Your impedance is made in the stack-up, not in the layout tool
From roughly a one nanosecond edge onwards a track behaves like a transmission line rather than a wire. Its wave impedance depends on the width, on the distance to the nearest reference plane and on the laminate. The most effective control is the distance: a thinner prepreg lowers the width required, and both are set by the fabricator, not by the layout tool.
A via conducts in its wall only
The current does not flow through the hole, it flows through the copper on its inner wall. A 0.3 mm hole with 25 µm of copper gives about 0.026 mm² of cross-section, less than a 0.8 mm track on an outer layer. That is exactly why several vias sit side by side wherever a power path changes layer.
Copper comes in steps only
Laminate is bought with the copper foil already bonded to it, in fixed weights: 18, 35, 70, 105, 140, 175 and 210 µm, which is 0.5 to 6 ounces per square foot. A calculator answering 47 µm answers with a thickness nobody can order. So this tool offers only the weights that can be delivered. If a shared link brings a different value anyway, it computes with that value and says that it cannot be ordered.
How this tool computes
Cross-section from current and rise
IPC-2221B, equation 6-4: the current is a constant times the temperature rise to the power 0.44 times the cross-section to the power 0.725. The equation is solved for the area.
Width from the cross-section
The area divided by the copper thickness. The constant is 0.048 on an outer layer and 0.024 on an inner one, because a buried track sheds its heat worse.
Impedance from the geometry
IPC-2141A: for the microstrip from width, copper thickness, height above the plane and dielectric constant, for the stripline from the same quantities with both planes.
The via as a ring
The barrel's cross-section is an annulus from hole diameter and plating thickness. After that the same equation as for the flat track applies again.
What this tool does not say
- The temperature rise holds for a single track in still air. Several current-carrying tracks side by side, or an assembly inside a closed housing, run hotter than computed here.
- The IPC-2221B curves are drawn for rises of 10 to 100 K. Outside that the tool keeps computing and says that it is extending the formula.
- The impedance equations hold for a single line over a continuous reference plane. Differential pairs, gaps in the plane and the effect of solder mask are not included.
- The dielectric constant is not a material constant. Resin content, glass style and frequency all move it, and the figure that counts is in the laminate datasheet.
- No result here replaces an impedance requirement given to the board fabricator. He lays out the stack-up with his own prepreg thicknesses and measures the finished build.
Where the arithmetic comes from
This is an IPC 2221 calculator in the strict sense: the equations are published in IPC-2221B and IPC-2141A and nothing here is a house rule. What PCBoffer adds is the line underneath, which makes it a copper weight calculator as well: which copper weights can be ordered and where the etch floor runs comes from the same rule set the costing core uses to judge an uploaded board for manufacturability. So that the free arithmetic cannot contradict the paid product, a check run holds the three calculators on this page against 14 hand-computed anchor points from the two standards.
Free: PCB panelisation calculator
How many boards fit on one panel, how large the panel becomes and how much area stays unused. No sign-up, computed in the browser, with the same physics the costing uses.
Calculate a panelFrequently asked questions
- How wide does a track have to be for 1 A?
- On an outer layer with 35 µm copper and a 10 K allowed rise it is about 0.30 mm. That is not a constant: it follows from the rise you allow, and at 20 K about 0.20 mm is enough. IPC-2221B prescribes no current density, it prescribes a temperature, and the width is the value at which heat generated and heat shed balance.
- Why does a track on an inner layer need more width than one on an outer layer?
- Because it can only shed heat through the laminate and not into the air as well. IPC-2221B models that with a constant half as large: 0.024 instead of 0.048. The width does not double as a result, it grows by about 2.6 times, because the exponent 0.725 sits between area and current. Which is why power belongs on the outside.
- Which copper weight is the right one?
- 35 µm is the standard and covers most boards. A heavier weight pays off when the computed width no longer fits the layout: 70 µm halves the width needed for the same current. Only fixed steps can be ordered, namely 18, 35, 70, 105, 140, 175 and 210 µm, because laminate is bought with the foil already bonded to it. What the heavier step costs is in the fabricator's quotation.
- How accurate is the IPC-2221 equation?
- It is a fit to measured curves and holds for a single track in still air, drawn for rises of 10 to 100 K. Several current-carrying tracks side by side, or an assembly in a closed housing, run hotter than computed. Outside the range of the curves this tool keeps computing and says that it is extending the formula.
- Why does my board fabricator give me a different width for 50 ohm?
- Because wave impedance depends on the whole stack-up and not on the width alone: prepreg thickness, resin content, glass style and frequency all move it. The fabricator lays out the stack with his own material thicknesses and measures the finished build. So give him the target impedance rather than the width; the width computed here is the starting point for your layout.
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